Fix printing of u64 value 'msr_content' to use PRIx64 format.

Signed-off-by: Keir Fraser <keir@xensource.com>

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 0b2a6765f18f367885ec3a2f734a72adba1eb517..106bfffef0bc25c91129d2c6e5b1c9f00b7226af 100644 (file)
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -298,13 +298,8 @@ static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
         return 0;
     }
 
-#ifdef __x86_64__
-    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n", 
-            msr_content);
-#else
-    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %llx\n", 
+    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n", 
             msr_content);
-#endif
 
     regs->eax = msr_content & 0xffffffff;
     regs->edx = msr_content >> 32;
@@ -317,13 +312,9 @@ static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
     struct vcpu *vc = current;
     struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
 
-#ifdef __x86_64__
-    HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx msr_content %lx\n", 
-                regs->ecx, msr_content);
-#else
-    HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %x msr_content %llx\n", 
-                regs->ecx, msr_content);
-#endif
+    HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx "
+                "msr_content %"PRIx64"\n", 
+                (unsigned long)regs->ecx, msr_content);
 
     switch (regs->ecx)
     {

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 5da0eff0d49c907f54bb83e8569e2d4edc052bf4..0e8a4f386e208d8218770692fd09c39b8636660b 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -172,7 +172,7 @@ static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
     switch(regs->ecx){
     case MSR_EFER:
         msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
-        HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content %llx\n", (unsigned long long)msr_content);
+        HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content %"PRIx64"\n", msr_content);
         if (test_bit(VMX_CPU_STATE_LME_ENABLED,
                      &vc->arch.hvm_vmx.cpu_state))
             msr_content |= 1 << _EFER_LME;
@@ -202,7 +202,8 @@ static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
     default:
         return 0;
     }
-    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n", msr_content);
+    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n",
+                msr_content);
     regs->eax = msr_content & 0xffffffff;
     regs->edx = msr_content >> 32;
     return 1;
@@ -216,8 +217,9 @@ static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
     struct vmx_msr_state * host_state =
         &percpu_msr[smp_processor_id()];
 
-    HVM_DBG_LOG(DBG_LEVEL_1, " mode_do_msr_write msr %lx msr_content %lx\n",
-                regs->ecx, msr_content);
+    HVM_DBG_LOG(DBG_LEVEL_1, " mode_do_msr_write msr %lx "
+                "msr_content %"PRIx64"\n",
+                (unsigned long)regs->ecx, msr_content);
 
     switch (regs->ecx){
     case MSR_EFER: